With regard to testing an LSI circuit (Large Scale Integrated circuits), a configuration is disclosed in Patent Document 1, for example, as shown in FIG. 9, where a non-defective LSI circuit 11 that has been confirmed in advance to be non-defective, and an LSI circuit 12 under measurement are synchronized and operated under identical test input conditions, and a determination is made as to whether or not the LSI circuit 12 under measurement performs an operation that is functionally identical to the non-defective LSI circuit 11.
Furthermore, with regard to an emulation device for performing emulation of a processor under test, as an in-circuit emulator (ICE) that performs emulation in realtime, a configuration is disclosed in Patent Document 2, for example, as shown in FIG. 10, which is provided with a storage means (trace memory unit) 5 that stores in advance reference data corresponding to an expected instruction execution result for a processor (MPU) 3 under test and that sequentially outputs reference data based on an external clock signal synchronous with an instruction execution cycle of the processor (MPU) 3 under test; a comparison means (comparator unit) 7 that compares the execution result of the processor (MPU) 3 under test and the output reference data; and a control means (controller) 4 that performs interruption and continuation of emulation based on a comparison result signal.
[Patent Document 1]
    JP Patent Kokai Publication No. JP-A-5-119116[Patent Document 2]    JP Patent Kokai Publication No. JP-A-5-73347